Thermally-isolated circuit elements have been developed and made in several ways. Reay et al (“Thermally and Electrically Isolated Single Crystal Silicon Structures in CMOS Technology” R. J. Reay, E. H. Klaassen, G. T. A. Kovacs, IEEE Electron Device Letters Vol. 15, No. 10, October 1994, pp. 399-401; U.S. Pat. No. 5,600,174 “Suspended Single Crystal Silicon Structures and Method of Making Same”), have shown that electrochemical etching of silicon can be used to create small masses of thermally-isolated silicon, in which circuit components could be housed. Such thermally-isolated circuit elements have the advantage that they can be heated independently of nearby circuit elements on the same chip or substrate. In this way, their operating temperature can be controlled independently without affecting the operation of other nearby circuit elements.
Reay et al's method of making such thermally-isolated silicon islands involves electrochemical etching of silicon, where electrodes need to be electrically connected to the islands while the device is in the etchant solution, and the islands are defined by a p-n junction implanted or diffused into the silicon. Also, others have demonstrated methods of processing silicon islands by other methods, such as “Digital MOS-Transistor-Based Microhotplate Array for Simultaneous Detection of Environmentally Relevant Gases” M. Graf, S. Taschini, P. Kaser, C. Hagleitner, A. Hierlemann, H. Baltes in the Proceedings of the MEMS 2004 Conference in Maastricht, January, 2004 p. 351, and M. Schneider, T. Muller, A. Haberli, M. Hornung, H. Baltes “Integrated Micromachined Decoupled CMOS Chip on Chip”, Proceedings IEEE—The Tenth Annual (1997) International Workshop on Micro Electro Mechanical Systems (Cat. No. 97CH36021), (1997) pp. 512-517.
In these cases, the open areas are defined, the silicon is wet-etched, but the etchant does not attack the silicon masses which are protected by electrochemical etch-stop. In this way, the etchant attacks underneath these protected silicon volumes, releasing the suspended silicon block and films above it from the substrate. However, it must be noted that electrochemically-based etch-stopping requires that a potential be applied to the island regions via electrical contacts, continually throughout the wet-etching process.
Other researchers (Ducso, Vazsonyi, Adam, Szabo, Barsony, Gardeniers, van den Berg “Porous silicon bulk micromachining for thermally isolated membrane formation”, Sensors and Actuators A 60 (1997) pp. 235-239; and U.S. Pat. No. 6,359,276 “Microbolometer infrared sensors”, Tu Xiang Zheng), have created released silicon masses by creating a porous silicon layer beneath the intended silicon masses, and then selectively etching away the porous silicon layer. Again, the creation of porous silicon involves an electrochemical anodization process, which requires potential to be applied via electrical contacts during a wet-etch process.
Using the methods known in the art, it is not possible to create such silicon islands without using an electrochemical process, which involves the need for electrical connection to the silicon wafer during wet processing.
Consider a typical suspended microstructure such as used in thermal sensors, or trimmable resistor as depicted in FIG. 1a and 1b of International publication No. WO 03/023794. Such microstructures are typically made in a {100}-oriented silicon wafer, and released (suspended) over a cavity, by a wet anisotropic etch of the silicon underneath the microstructures. The cavity is etched along crystallographic surfaces governed by the anisotropy of the wet etch. Concave configurations tend to be bounded by slow-etch surfaces (usually {111}-family silicon surfaces), while convex configurations tend to be bounded by fast-etch surfaces. If the open silicon area is a simple rectangle (without any suspended microstructures), with the sides of the rectangle aligned with the intersection of {111} surfaces and the {100} wafer surface, then all of the silicon surfaces and surface-intersections inside the cavity will be generally flat or concave, and the resulting cavity will be bounded by only the downward-etching {100} surface, and {111}-family surfaces inclined at 54.7° from the wafer surface. Even if the open silicon area is not a rectangle, or not aligned as described above, then if one etches long enough, the resulting cavity will still intersect the surface in a rectangular pattern, bounded by {111}-family surfaces, which will be the outermost rectangle circumscribing the entire open silicon area.
When there are microstructures intended to be released (suspended) over the etched cavity, these microstructures must, by their presence, initially cover part of the surface of the silicon. In order for such a microstructure to be released, its shape must have certain features, such that it will be rapidly under-etched by etching of fast-etch surfaces underneath. For example, in the release of the three suspended microstructures shown in FIG. 2, the under-etching of the microstructures begins at the indicated convex points labeled “A”. Also, microstructures whose edges are not aligned parallel to the intersection of {111}-family surfaces with the {100} wafer surface, such as at the locations labeled “B”, will under-etch faster than {111}-family surfaces. In the case of the locations marked “B” in FIG. 2, the microstructure edges are aligned at roughly 45° from the intersection of {111}-family surfaces with the {100} wafer surface, and therefore will under-etch as either vertical {100}-family surfaces or 45°-inclined {110}-family surfaces, both much faster than the {111} (B. Nikpour, L. M. Landsberger, T. J. Hubbard, M. Kahrizi, A. Iftimie, “Concave Corner Compensation Between Vertical (010)-(001) Surfaces Anisotropically Etched in Si(100),” Sensors and Actuators A: Physical, Vol. 66/1-3, pp. 299-307 April 1998.)
At each convex location such as points “A”, there will typically appear two fast-etch surfaces, intersecting at a sharp convex edge as shown in FIG. 3. At locations such as points “B”, the portions of the microstructures will be relatively quickly under-etched, and the resulting structure will transform into a convex configuration with fast-etch surfaces intersecting at points such as the locations marked “C” in FIG. 2.
During the process of release (under-etch) of the microstructures, if there is stress in the films composing the microstructures, the already-released portions may bend, upward or downward, while the still-unreleased portions will be held fixed on the not-yet-etched silicon. Since the microstructures are most-often in the process of being released by under-etching at convex corners, and since these convex corners may be sharp, there may be severe concentration of stress at those points, which may lead to cracking of the microstructure layers. Therefore catastrophic damage (etching) of the embedded conductive traces may ensue, depending on where the cracks occur relative to the positions of the embedded conductors. (Ref: B. Nikpour, S. Naseh, L. M. Landsberger, M. Kahrizi, M. Paranjape, R. Antaki, J. F. Currie, “Release-Control Structures for Cantilever-Based Sensors,” Sensors and Materials, Vol. 10, No. 5, pp. 287-296, October 1998.) Alternatively, at or near the end of the release process, the silicon underneath the microstructures may be sharp-pointed, and agitation of the etch solution may cause damaging impact with the microstructure. (Ref: O. Grudin, R. Marinescu, L. M. Landsberger, D. Cheeke, M. Kahrizi, “CMOS-Compatible High-Temperature Micro-Heater: Microstructure Release and Testing,” Canadian Journal of Elec. and Comp. Engineering, Vol. 25, No. 1 pp. 29-34, (2000).)
Therefore, there is a need for a different etching technique, which reduces the risk of damage to the microstructure during the release process.